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PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
Rev. 04 -- 18 August 2009 Product data sheet
1. General description
The PCA9513A and PCA9514A are hot swappable I2C-bus and SMBus buffers that allow I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9513A and PCA9514A provides bidirectional buffering, keeping the backplane and card capacitances isolated. Rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9513A and PCA9514A incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a Low current mode when asserted LOW, and an open-drain READY output pin, which indicates that the backplane and card sides are connected together (HIGH) or not (LOW). The PCA9513A supplies a 92 A current source to SCLIN and SDAIN pins in lieu of using pull-up resistors which is ideal for multidrop bus applications. Including the current source in the device provides for a consistent RC time constant as cards are removed and inserted into the backplane. The current source is high-impedance whenever the pin voltage is greater than the part VCC. The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V to provide better noise margin over the PCA9511A which is set to 0.6 V. Remark: The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18 or PCA9517 B side or P82B96 Sx/y side.
2. Features
I Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems I Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards I Built-in V/t rise time accelerators on all SDA and SCL lines (0.8 V threshold) requires the bus pull-up voltage and supply voltage (VCC) to be the same I Rise time accelerator threshold moved from 0.6 V to 0.8 V for improved noise margin I Active HIGH ENABLE input I Active HIGH READY open-drain output I High-impedance SDAn and SCLn pins for VCC = 0 V
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
I 92 A current source on SCLIN and SDAIN for PICMG backplane applications (PCA9513A only) I Supports clock stretching and multiple master arbitration and synchronization I Operating power supply voltage range: 2.7 V to 5.5 V I 0 Hz to 400 kHz clock frequency I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8, TSSOP8 (MSOP8)
3. Applications
I cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system
4. Feature selection
Table 1. Feature Idle detect High-impedance SDAn, SCLn pins for VCC = 0 V Rise time accelerator circuitry on SDAn and SCLn pins Rise time accelerator circuitry hardware disable pin for lightly loaded systems Rise time accelerator threshold 0.8 V versus 0.6 V improves noise margin READY open-drain output Feature selection chart PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes -
Two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDAn and SCLn pins 92 A current source on SCLIN and SDAIN for PICMG applications in only -
5. Ordering information
Table 2. Ordering information Tamb = -40 C to +85 C Type number PCA9513AD PCA9514AD PCA9513ADP PCA9514ADP
[1]
Topside mark PA9513A PA9514A 9513A 9514A
Package Name SO8 SO8 TSSOP8[1] TSSOP8[1] Description plastic small outline package; 8 leads; body width 3.9 mm plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 SOT96-1
plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1
Also known as MSOP8.
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
2 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
Standard packing quantities and other packaging data are available at www.standardics.nxp.com/packaging/.
6. Block diagram
PCA9513A
92 A 2 mA 2 mA
OVERVOLTAGE CUT-OFF SDAIN
SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT
SLEW RATE DETECTOR
VCC SDAOUT
CONNECT
92 A
2 mA
2 mA
OVERVOLTAGE CUT-OFF SCLIN
SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT
SLEW RATE DETECTOR SCLOUT CONNECT 0.55VCC/ 0.45VCC STOP BIT AND BUS IDLE
0.5 A
0.55VCC/ 0.45VCC
20 pF
CONNECT 100 s DELAY UVLO READY RD S QB GND
UVLO ENABLE
0.5 pF
CONNECT
002aab680
Fig 1.
Block diagram of PCA9513A
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
3 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
PCA9514A
2 mA 2 mA
SLEW RATE DETECTOR SDAIN CONNECT BACKPLANE-TO-CARD CONNECTION
SLEW RATE DETECTOR
VCC SDAOUT
CONNECT
2 mA
2 mA
SLEW RATE DETECTOR SCLIN CONNECT BACKPLANE-TO-CARD CONNECTION
SLEW RATE DETECTOR SCLOUT CONNECT 0.55VCC/ 0.45VCC STOP BIT AND BUS IDLE
0.5 A
0.55VCC/ 0.45VCC
20 pF
CONNECT 100 s DELAY UVLO READY RD S QB GND
UVLO ENABLE
0.5 pF
CONNECT
002aab681
Fig 2.
Block diagram of PCA9514A
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
4 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
7. Pinning information
7.1 Pinning
ENABLE SCLOUT SCLIN GND
1 2 3 4
002aab676
8
VCC SDAOUT SDAIN READY
ENABLE SCLOUT SCLIN GND
1 2 3 4
002aab677
8
VCC SDAOUT SDAIN READY
PCA9513AD PCA9514AD
7 6 5
PCA9513ADP PCA9514ADP
7 6 5
Fig 3.
Pin configuration for SO8
Fig 4.
Pin configuration for TSSOP8 (MSOP8)
7.2 Pin description
Table 3. Symbol ENABLE Pin description Pin 1 Description Chip enable. Grounding this input puts the part in a Low current (< 1 A) mode. It also disables the rise time accelerators, isolates SDAIN from SDAOUT and isolates SCLIN from SCLOUT. serial clock output to and from the SCL bus on the card serial clock input to and from the SCL bus on the backplane Ground. Connect this pin to a ground plane for best results. open-drain output which pulls LOW when SDAIN and SCLIN are disconnected from SDAOUT and SCLOUT, and goes HIGH when the two sides are connected serial data input to and from the SDA bus on the backplane serial data output to and from the SDA bus on the card power supply
SCLOUT SCLIN GND READY
2 3 4 5
SDAIN SDAOUT VCC
6 7 8
8. Functional description
Refer to Figure 1 "Block diagram of PCA9513A" and Figure 2 "Block diagram of PCA9514A".
8.1 Start-up
An undervoltage and initialization circuit holds the parts in a disconnected state which presents high-impedance to all SDAn and SCLn pins during power-up. A LOW on the ENABLE pin also forces the parts into the low current disconnected state when the ICC is essentially zero. As the power supply is brought up and the ENABLE is HIGH or the part is powered and the ENABLE is taken from LOW to HIGH it enters an initialization state where the internal references are stabilized and the 92 A input pull-ups (on the PCA9513A) is enabled. At the end of the initialization state the `Stop Bit And Bus Idle' detect circuit is enabled. With the ENABLE pin HIGH long enough to complete the initialization state (ten) and remaining HIGH when all the SDAn and SCLn pins have been
PCA9513A_PCA9514A_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
5 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
HIGH for the bus idle time or when all pins are HIGH and a STOP condition is seen on the SDAIN and SCLIN pins, SDAIN is connected to SDAOUT and SCLIN is connected to SCLOUT. A 92 A pull-up current source on SDAIN and SCLIN of the PCA9513A is activated during the initialization state and remains active until the power is removed or the ENABLE pin is taken LOW. When the 92 A pull-up is active it will become high-impedance any time the pin voltage is greater than VCC, otherwise it provides current to pull the pin up to VCC.
8.2 Connect circuitry
Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the part. The same is also true for the SCLn pins. Noise between 0.7VCC and VCC is generally ignored because a falling edge is only recognized when it falls below 0.7VCC with a slew rate of at least 1.25 V/s. When a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. The driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the first falling pin is below 0.7VCC. The first falling pin may have a fast or slow slew rate, if it is faster than the pull-down slew rate then the initial pull-down rate will continue. If the first falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage then they will both continue down at the slew rate of the first. Once both sides are LOW they will remain LOW until all the external drivers have stopped driving LOWs. If both sides are being driven LOW to the same value for instance, 10 mV by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise until the internal driver pulls it down to the offset voltage. When the last external driver stops driving a LOW, that pin will rise up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25 V/s, when the pin voltage exceeds 0.8 V for the PCA9513A and PCA9514A, the rise time accelerators' circuits are turned on and the pull-down driver is turned off.
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher temperatures. Maximum offset voltage (Voffset) is 0.150 V with a 10 k pull-up resistor. The LOW level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if lightly loaded the VOL may be ~0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V, the level after four buffers would be 0.5 V, which is only about 0.3 V below the threshold of the rising edge accelerator (about 0.8 V). With great care a system with four buffers may work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset.
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
6 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected.
buffer A MASTER common node
buffer B SLAVE B
buffer C SLAVE C
002aab581
Fig 5.
System with 3 buffers connected to common node
Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of buffer A and buffer B in series as shown in Figure 5. Consider if the VOL at the input of buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change you would observe VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the input of buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node will rise to 0.5 V before buffer B's output turns on, if the pull-up is strong the node may bounce. If the bounce goes above the threshold for the rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire contending with the output of buffer B. The node on the input of buffer A will go HIGH as will the input node of buffer C. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~0.5 V because the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to ~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on buffer A and buffer C would see a false clock rather than a stretched clock, which would cause a system error. The PCA9513A and PCA9514A rise time accelerator threshold is 0.8 V, so there is 0.2 V more noise margin.
8.4 Propagation delays
The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same.
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
7 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
The tPHL can never be negative because the output does not start to fall until the input is below 0.7VCC, and the output turn on has a non-zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL occurs when the input is driven LOW with zero delay and the output is still limited by its turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, VCC and process, as well as the load current and the load capacitance.
8.5 Rise time accelerators
During positive bus transitions a 2 mA current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.8 V for the PCA9513A and PCA9514A are exceeded. The rising edge rate should be at least 1.25 V/s to guarantee turn on of the accelerators. The built-in V/t rise time accelerators on all SDA and SCL lines requires the bus pull-up voltage and supply voltage (VCC) to be the same.
8.6 READY digital output
This pin provides a digital flag which is LOW when either ENABLE is LOW or the start-up sequence described earlier in this section has not been completed. READY goes HIGH when ENABLE is HIGH and start-up is complete. The pin is driven by an open-drain pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of 10 k to VCC to provide the pull-up.
8.7 ENABLE low current disable
Grounding the ENABLE pin disconnects the backplane side from the card side, disables the rise time accelerators, drives READY LOW, disables the bus precharge circuitry, and puts the part in a low current state. When the pin voltage is driven all the way to VCC, the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides.
8.8 Resistor pull-up value selection
The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/s on the SDAn and SCLn pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula given in Equation 1:
3 V CC ( min ) - 0.6 R PU 800 x 10 ---------------------------------- - C
(1)
where RPU is the pull-up resistor value in , VCC(min) is the minimum VCC voltage in volts, and C is the equivalent bus capacitance in picofarads. In addition, regardless of the bus capacitance, always choose RPU 65.7 k for VCC = 5.5 V maximum, RPU 45 k for VCC = 3.6 V maximum. The start-up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figure 6 and Figure 7 for guidance in resistor pull-up selection.
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
8 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
50 RPU (k) 40
(1)
002aae780
Rmax = 45 k
30 rise time = 300 ns(2) 20 rise time = 20 ns 10 Rmin = 1 k 0 0 100 200 300 Cb (pF) 400
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9513A/PCA9514A. (2) Rise time without PCA9513A/PCA9514A.
Fig 6.
Bus requirements for 3.3 V systems
002aae781
70 RPU (k) 60 50
(1)
Rmax = 65.7 k
40 rise time = 300 ns(2) 30 20 rise time = 20 ns 10 Rmin = 1.7 k 0 0 100 200 300 Cb (pF) 400
(1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with PCA9513A/PCA9514A. (2) Rise time without PCA9513A/PCA9514A.
Fig 7.
Bus requirements for 5 V systems
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
9 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
8.9 Hot swapping and capacitance buffering application
Figure 8 through Figure 11 illustrate the usage of the PCA9513A and PCA9514A in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise and fall time requirements difficult to meet. Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9513A and PCA9514A drive the capacitance of everything on the card, and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, `Hot Swap Bus Buffer' for more information on applications and technical assistance.
BACKPLANE CONNECTOR
BACKPLANE STAGGERED CONNECTOR VCC
R1 10 k R2 10 k
I/O PERIPHERAL CARD 1 POWER SUPPLY HOT SWAP
R3 10 k C1 0.01 F
R4 10 k
R5 10 k
R6 10 k
BD_SEL SDA SCL
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD1_SDA CARD1_SCL
I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R7 10 k C3 0.01 F
R8 10 k
R9 10 k
R10 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD2_SDA CARD2_SCL
I/O PERIPHERAL CARD N STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R11 10 k C5 0.01 F
R12 10 k
R13 10 k
R14 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARDN_SDA CARDN_SCL
002aab584
Remark: The PCA9514A can be used in any combination depending on the number of rise time accelerators that are needed by the system. Normally only one PCA9514A would be required per bus.
Fig 8.
Hot swapping multiple I/O cards into a backplane using the PCA9514A in a cPCI, VME, and AdvancedTCA system
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
10 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
BACKPLANE CONNECTOR
BACKPLANE STAGGERED CONNECTOR VCC POWER SUPPLY HOT SWAP
I/O PERIPHERAL CARD 1
C1 0.01 F
R1 10 k
R2 10 k
R3 10 k
R4 10 k
BD_SEL SDA SCL
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD1_SDA CARD1_SCL
I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R5 10 k C3 0.01 F
R6 10 k
R7 10 k
R8 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD2_SDA CARD2_SCL
I/O PERIPHERAL CARD N STAGGERED CONNECTOR POWER SUPPLY HOT SWAP
R9 10 k C5 0.01 F
R10 10 k
R11 10 k
R12 10 k
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARDN_SDA CARDN_SCL
002aab678
Fig 9.
Hot swapping multiple I/O cards into a backplane using the PCA9513A in a cPCI, VME, and AdvancedTCA system
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
11 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
BACKPLANE CONNECTOR
BACKPLANE VCC
R1 10 k R2 10 k
I/O PERIPHERAL CARD 1 STAGGERED CONNECTOR
C1 0.01 F
R4 10 k
R5 10 k
R6 10 k
SDA SCL
C2 0.01 F
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD1_SDA CARD1_SCL
I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR
C3 0.01 F
R8 10 k
R9 10 k
R10 10 k
C4 0.01 F
ENABLE SDAIN SCLIN
VCC
GND
SDAOUT SCLOUT READY
CARD2_SDA CARD2_SCL
002aab585
Fig 10. Hot swapping multiple I/O cards into a backplane using the PCA9514A in a PCI system
Rdrop
VCC
R1 10 k R4 10 k
VCC_LOW
C2 0.01 F R2 10 k R3 10 k R5 10 k
SDA SCL
VCC ENABLE SDAOUT SDAIN SCLOUT SCLIN READY GND
SDA2 SCL2
002aab587
VCC > VCC_LOW. Rdrop is the line loss of VCC in the backplane.
Fig 11. System with disparate VCC voltages
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
12 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
9. Application design-in information
VCC (2.7 V to 5.5 V) 8 SCLIN 3
C1 0.01 F
R5 10 k
R3 10 k
R4 10 k
2
SCLOUT
SDAIN
6
7
SDAOUT
ENABLE
1
ENABLE GND 4
READY
5
002aab679
Fig 12. Typical application of PCA9513A
VCC (2.7 V to 5.5 V)
R1 10 k
R2 10 k
C1 0.01 F
8
R5 10 k
R3 10 k
R4 10 k
SCLIN
3
2
SCLOUT
SDAIN
6
7
SDAOUT
ENABLE
1
ENABLE GND 4
READY
5
002aab579
Fig 13. Typical application of PCA9514A
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
13 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
10. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC Vn Toper Tstg Tsp Tj(max)
[1]
Parameter supply voltage voltage on any other pin operating temperature storage temperature solder point temperature maximum junction temperature
Conditions
[1] [1]
Min -0.5 -0.5 -40 -65
Max +7 +7 +85 +150 300 125
Unit V V C C C C
10 s max.
-
Voltages with respect to pin GND.
11. Characteristics
Table 5. Characteristics VCC = 2.7 V to 5.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VCC ICC ICC(sd) Parameter supply voltage supply current Shut-down mode supply current HIGH-level input voltage on pin ENABLE LOW-level input voltage on pin ENABLE input current on pin ENABLE enable time bus idle time to READY active disable time (ENABLE to READY) SDAIN to READY delay after STOP SCLOUT/SDAOUT to READY delay off-state leakage current on pin READY input capacitance on pin ENABLE output capacitance on pin READY LOW-level output voltage on pin READY VENABLE = VCC VI = VCC or GND VI = VCC or GND Ipu = 3 mA; VENABLE = VCC
[4] [3]
Conditions
[1]
Min 2.7 -
Typ 3.5 16
Max 5.5 6 -
Unit V mA A
Power supply VCC = 5.5 V; VSDAIN = VSCLIN = 0 V VENABLE = 0 V; all other pins at VCC or GND
[1]
Start-up circuitry VIH(ENABLE) VIL(ENABLE) II(ENABLE) ten tidle(READY) tdis(EN-RDY) tstp(READY) tREADY ILZ(READY) Ci(ENABLE) Co(READY) VOL(READY) 0.3 x VCC VENABLE = 0 V to VCC
[2] [1]
0.5 x VCC 0.7 x VCC V 0.5 x VCC 0.1 110 105 30 1.3 0.8 0.3 1.9 2.5 0.04 1 200 4.0 4.0 0.4 V A s s ns s s A pF pF V
50 -
[3]
[4]
[1]
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
14 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
Table 5. Characteristics ...continued VCC = 2.7 V to 5.5 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Itrt(pu) Parameter transient boosted pull-up current Conditions positive transition on SDA, SCL; VCC = 2.7 V; slew rate = 1.25 V/s 10 k to VCC on SDA, SCL; VCC = 3.3 V SCL to SCL and SDA to SDA; 10 k to VCC; CL = 100 pF each side SCL to SCL and SDA to SDA; 10 k to VCC; CL = 100 pF each side
[4] [5][6]
Min 1
Typ 2
Max -
Unit mA
Rise time accelerators
Input-output connection Voffset tPLH offset voltage LOW to HIGH propagation delay
[1][7][9]
0 -
118 20
175 -
mV ns
tPHL
HIGH to LOW propagation delay
-
80
-
ns
Ci(SCL/SDA) VOL
SCL and SDA input capacitance LOW-level output voltage VI = 0 V; SDAn, SCLn pins; Isink = 3 mA; VCC = 2.7 V VENABLE = VCC; PCA9513A only VENABLE = VCC; PCA9513A only SDAn, SCLn pins; VCC = 5.5 V
0
6 0.3
8 0.4
pF V
[1]
Ipu(SCLIN) Ipu(SDAIN) ILI
pull-up current on pin SCLIN pull-up current on pin SDAIN input leakage current
[9]
65 65 -1
112 112 -
150 150 +1
A A A
[9]
System characteristics fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tf tr SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals
This specification applies over the full operating temperature range. The enable time can slow considerably for some parts when temperature is < -20 C.
(c) NXP B.V. 2009. All rights reserved.
[4] [4]
0 1.3 0.6 0.6 0.6 300 100 1.3 0.6
-
400 300 300
kHz s s s s ns ns s s ns ns
[4]
[4]
[4]
[4] [4] [4] [4] [4][8]
20 + 0.1 x Cb 20 + 0.1 x Cb -
[4][8]
[1] [2]
PCA9513A_PCA9514A_4
Product data sheet
Rev. 04 -- 18 August 2009
15 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
[3] [4] [5] [6] [7] [8] [9]
Delays that can occur after ENABLE and/or idle times have passed. Guaranteed by design, not production tested. Itrt(pu) varies with temperature and VCC voltage, as shown in Section 11.1 "Typical performance characteristics". Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in Section 11.1 "Typical performance characteristics". Cb = total capacitance of one bus line in pF. Force VSDAIN = VSCLIN = 0.1 V, tie SDAOUT and SCLOUT through 10 k resistor to VCC and measure the SDAOUT and SCLOUT output.
11.1 Typical performance characteristics
3.7 ICC (mA) 3.3
002aab588
12 Itrt(pu) (mA) 8
002aab590
VCC = 5.5 V
3.3 V 2.7 V
VCC = 5 V
2.9
4 3.0 V 2.7 V
2.5 -40
+25 Tamb (C)
+90
0 -40
+25 Tamb (C)
+90
Fig 14. ICC versus temperature
90 VCC = 5.5 V tPHL (ns) 80
002aab589
Fig 15. Itrt(pu) versus temperature
350 V O - VI (mV) 250
002aab591
2.7 V 3.3 V
70
150 VCC = 5 V 3.3 V
60 -40
50 +25 Tamb (C) +90 0 10 20 30 RPU (k) 40
Ci = Co > 100 pF; RPU(in) = RPU(out) = 10 k
Fig 16. Input/output tPHL versus temperature
Fig 17. Connection circuitry VO - VI
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
16 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
11.2 Timing diagrams
SDAn/SCLn
ten ENABLE tidle(READY) READY
002aab592
tdis
Fig 18. Timing for ten, tidle(READY), and tdis
SDAIN
SCLIN SCLOUT SDAOUT ten ENABLE tstp(READY) READY
002aab593
tstp(READY) is only applicable after the ten delay.
Fig 19. tstp(READY) that can occur after ten
SCLIN, SDAIN, SCLOUT, SDAOUT ten tidle(READY) ENABLE tstp(READY) READY
002aab594
tstp(READY) is only applicable after the ten delay.
Fig 20. tstp(READY) delay that can occur after ten and tidle(READY)
PCA9513A_PCA9514A_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
17 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
12. Test information
VCC VCC PULSE GENERATOR VI DUT
RT CL 100 pF RL 10 k
VO
002aab595
RL = load resistor CL = load capacitance includes jig and probe capacitance RT = termination resistance should be equal to the output impedance Zo of the pulse generator
Fig 21. Test circuitry for switching times
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
18 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
13. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 22. Package outline SOT96-1 (SO8)
PCA9513A_PCA9514A_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
19 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 23. Package outline SOT505-1 (TSSOP8)
PCA9513A_PCA9514A_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
20 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
PCA9513A_PCA9514A_4 (c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
21 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7
Table 6. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 7. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
22 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
15. Abbreviations
Table 8. Acronym AdvancedTCA CDM cPCI DUT ESD HBM I2C-bus MM PCI PICMG SMBus VME Abbreviations Description Advanced Telecommunications Computing Architecture Charged-Device Model compact Peripheral Component Interface Device Under Test ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Machine Model Peripheral Component Interface PCI Industrial Computer Manufacturers Group System Management Bus VERSAModule Eurocard
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
23 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
16. Revision history
Table 9. Revision history Release date 20090818 Data sheet status Product data sheet Change notice 2nd Supersedes PCA9513A_PCA9514A_3 Document ID PCA9513A_PCA9514A_4 Modifications:
*
Section 8.8 "Resistor pull-up value selection", paragraph, 1st sentence changed from "... always choose RPU 16 k for VCC = 5.5 V maximum, RPU 24 k for VCC = 3.6 V maximum." to "always choose RPU 65.7 k for VCC = 5.5 V maximum, RPU 45 k for VCC = 3.6 V maximum." Figure 6 "Bus requirements for 3.3 V systems" updated: - changed from "rise time > 300 ns" to "rise time = 300 ns" - changed from "rise time < 20 ns" to "rise time = 20 ns"
*
*
Figure 7 "Bus requirements for 5 V systems" updated: - changed from "rise time > 300 ns" to "rise time = 300 ns" - changed from "rise time < 20 ns" to "rise time = 20 ns"
PCA9513A_PCA9514A_3 PCA9513A_PCA9514A_2 PCA9513A_PCA9514A_1
20090720 20090528 20051011
Product data sheet Product data sheet Product data sheet
-
PCA9513A_PCA9514A_2 PCA9513A_PCA9514A_1 -
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
24 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9513A_PCA9514A_4
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 -- 18 August 2009
25 of 26
NXP Semiconductors
PCA9513A; PCA9514A
Hot swappable I2C-bus and SMBus bus buffer
19. Contents
1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 9 10 11 11.1 11.2 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 5 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 6 Maximum number of devices in series . . . . . . . 6 Propagation delays . . . . . . . . . . . . . . . . . . . . . . 7 Rise time accelerators . . . . . . . . . . . . . . . . . . . 8 READY digital output . . . . . . . . . . . . . . . . . . . . 8 ENABLE low current disable. . . . . . . . . . . . . . . 8 Resistor pull-up value selection . . . . . . . . . . . . 8 Hot swapping and capacitance buffering application. . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application design-in information . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 Typical performance characteristics . . . . . . . . 16 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 17 Test information . . . . . . . . . . . . . . . . . . . . . . . . 18 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 August 2009 Document identifier: PCA9513A_PCA9514A_4

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